In recent years, the PRML (partial response most-likelihood) method is utilized in systems for processing read signals in optical disk drives such as for DVD (digital versatile disc). This read method is already widely used in the communications field and information recording devices such as magnetic tape units and hard disk drives and so is a convenient method for achieving low bit error rates even under conditions where there is strong inter-symbol interference. Therefore this PRML method is particularly effective for boosting the linear recording density.
The discussion for the present invention is mainly focused on signals whose minimum run length is 2 T, which is utilized in the Blu-ray disc; unless specified otherwise, the minimum run length is assumed as 2 T. A signal subjected to AD (analog-to-digital) signal conversion is mainly used. Therefore, from hereon unless specified otherwise, a signal referred to simply as a read signal indicates AD converted data. However, when not clearly indicated in the text, the read signal need not always be AD converted data.
The typical structure of a read circuit for an optical disk using PRML signal processing is shown in FIG. 2. This type of circuit is disclosed for example in JP-A No. 298514/2002. In this figure, the read signal acquired from the optical head is converted to a digital data stream by the AD converter 21, after being subjected AGC (automatic gain control) equalization, and elimination of DC components by an analog signal processor 10. A slicer 22 minimizes the DC components occurring due to pattern dependence. Next, after equalization performed as needed by a FIR (finite impulse response) equalizer 23, the signal is input to the Viterbi decoder 40 and is here binarized. The PRML signal processing system operates using a clock signal synchronized to the read signal clock as its reference, and therefore uses a PLL (phase-locked loop) to synchronize the signal processing system clock to the phase of the read signal. As shown in FIG. 2, a digital-PLL utilizing a phase detector 31 with the digital method, is generally utilized when inputting the signal to the PLL after conversion in the ADC (analog-to-digital converter). In the example in FIG. 2, a PLL 30 includes a phase detector 31, a loop filter 33, and a VCO (voltage controlled oscillator) 34. The phase detector 31 compares the input signal with the phase of the clock 52 generated by the VCO34, and generates a phase error.